<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="dsp_fpga_project" device="LFE5U-25F-7BG256I" default_implementation="impl1">
    <Options/>
    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="my">
        <Options def_top="top"/>
        <Source name="src/tb.vhd" type="VHDL" type_short="VHDL" syn_sim="SimOnly">
            <Options/>
        </Source>
        <Source name="src/top.vhd" type="VHDL" type_short="VHDL">
            <Options top_module="top"/>
        </Source>
        <Source name="src/downconvert.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/iir1.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/iir2.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/iir3.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/iir4.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/iir5.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/iir6.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/iir7.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/downsampl.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/detect.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/ctrl.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="src/graphics.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="pll/pll.sbx" type="sbx" type_short="SBX">
            <Options/>
        </Source>
        <Source name="constr.ldc" type="LSE Design Constraints File" type_short="LDC">
            <Options/>
        </Source>
        <Source name="dsp_fpga_project.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
        <Source name="sim/sim.spf" type="Simulation Project File" type_short="SPF">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="my" file="my.sty"/>
    <Strategy name="my2" file="my2.sty"/>
</BaliProject>
